Instruction set docs: https://cdrdv2-public.intel.com/843860/architecture-instruction-set-extensions-programming-reference-dec-24.pdf

Will prefetch (load before needed) data into #D-cache.

Will prefetch (load before needed) data into #D-cache.

Will prefetch (load before needed) data into #D-cache.

Will prefetch (load before needed) data into #D-cache for a write.

Will prefetch (load before needed) instructions into #I-cache.

Write to #Model-Specific Register (MSR) by default)

Write to #Model-Specific Register (MSR).

a Model-Specific Register (MSR) is a special control register used by the CPU to manage its own features. Think of MSRs as the CPU's internal "settings panel." They control everything from performance monitoring counters and thermal sensors to enabling or disabling advanced features. The standard instruction to write to these registers has always been WRMSR.

A serializing instruction will wait until all buffer are written before running and ensure that it runs alone on the core (no parallel task).

Cache L1,2,3 are cache inside the CPU. L1 being the smallest but faster and L3 being biggest and slowest.

This cache will contain:

Data cache, there to cache data to be processed.

Instruction cache, Contains instruction to be ran.