RiscV

Terms:

Page Table Entry (PTE)

PTE is an entry that tells where in physical memory a given page is. it also contain permissions for said page.

wayyy more here: [1]

hart

Hardware thread

STD:

Extensions:

BF16

bfloat16 (brain floating point) floating-point format is a computer number format occupying 16 bits. Made for AI and it uses: Zfbfmin, Zvfbfmin and Zvfbfwma check page 159

Zicbom

Cache management operations check page 213

Zaamo

Atomic Memory operations check page 97

Zalrsc

Load-Reserved/Store-Conditional Instructions check page 92

Zicntr

Base Counters and Timers check page 73

Zihpm

Hardware Performance Counters check page 76

ZKR

The entropy source extension defines the seed CSR at address 0x015. This CSR provides up to 16

physical entropy bits that can be used to seed cryptographic random bit generators.

SVVPTC

ratified Jun 29, 2024 and added in linux 6.12. Obviating Memory-Management Instructions after Marking PTEs Valid

Smmpm

Smnpm

Ssnpm

All instruction to use pointer masking at different levels[2]

Sources:


  1. : RISC-V Page Table I - Simon Sun

  2. : https://raw.githubusercontent.com/riscv/riscv-j-extension/master/zjpm-spec.pdf