RiscV

Modes/Privilege levels

  • Machine Mode (M-mode): This is the highest privilege level. It has full control over the hardware. The firmware that starts the computer runs in this mode. Also, uses only physical addresses.[3]
  • Supervisor Mode (S-mode): This is a less privileged level where the operating system kernel runs (Kernel mode).
  • User Mode (U-mode): This is the lowest privileged level where the user/processes run (User mode)

Terms:

Page Table Entry (PTE)

PTE is an entry that tells where in physical memory a given page is. it also contain permissions for said page.

wayyy more here: [1]

hart

Hardware thread

Supervisor Binary Interface (SBI)

The SBI provides a standardized communication channel for communication from S-mode to M-mode. Can do things like shutting down the system, sending messages between processor cores (harts), or managing power states.[5]

FWFT

Firmware Features Extension allows the operating system (in S-mode) to control or ask about specific features handled by the firmware (M-mode) through the #Supervisor Binary Interface (SBI). [4]

Non exhaustive list of things that can be controlled using FWFT:

  • Shadow Stack
  • Hardware updating of Page Table Entry (PTE) A/D bits: This allows the hardware itself to mark memory pages as "Accessed" or "Dirty," which can make memory management in the OS more efficient.
  • Pointer Masking: Adds security bits to pointers, prevent certain types of memory corruption attacks.

TLDR the FWFT extension provides a standard way for Linux to ask the firmware for support and to turn on a feature.

STD:

Extensions:

BF16

bfloat16 (brain floating point) floating-point format is a computer number format occupying 16 bits. Made for AI and it uses: Zfbfmin, Zvfbfmin and Zvfbfwma check page 159

Zicbom

Cache management operations check page 213

Zaamo

Atomic Memory operations check page 97

Zalrsc

Load-Reserved/Store-Conditional Instructions check page 92

Zicntr

Base Counters and Timers check page 73

Zihpm

Hardware Performance Counters check page 76

ZKR

The entropy source extension defines the seed CSR at address 0x015. This CSR provides up to 16

physical entropy bits that can be used to seed cryptographic random bit generators.

SVVPTC

ratified Jun 29, 2024 and added in linux 6.12. Obviating Memory-Management Instructions after Marking PTEs Valid

Smmpm

Smnpm

Ssnpm

All instruction to use pointer masking at different levels[2]

Svinval

Used for fine-grained TLB invalidation. Without Svinval you would use something like SFENCE.VMA which will often invalidate way more that the TLB entry that you are targeting. Svinval is more precise.[6]

Zicbop

Cache-Block Operations Prefetch.Provides a standard way for software to give these prefetching hints to the hardware. It adds new instructions like PREFETCH.R (prefetch for a future read) and PREFETCH.W (prefetch for a future write).[6]

Zabha

Byte and Half-word Atomic. Adds atomic operations for Byte and Half-word (16 bits).[6]

SiFive

SiFive is an American fabless designer of RISC-V CPU, they make their own extensions:

Matrix Multiplication Instructions

xsfvqmaccdod, xsfvqmaccqoq, xsfvfwmaccqqq

Matrix multiplication is the mathematical foundation of modern neural networks. Having dedicated instructions to speed this up can provide a massive performance boost for AI tasks.[7]

FP32-to-INT8 Ranged Clip Instructions

xsfvfnrclipxfqf

In AI, it's common to use different numerical precisions. This instruction helps efficiently convert 32-bit floating-point numbers to 8-bit integers, a crucial step in optimizing AI models for inference.[7]

Sources: