Compute Express Link (CXL)

HDM

Host-managed-Device-Memory[1]

DVSEC

Designated Vendor-specific [2]

Shared Upstream Link Calculation

For certain CXL region construction with endpoints behind CXL switches (SW) or Root Ports (RP), there is the possibility of the total bandwidth for all the endpoints behind a switch being more than the switch upstream link. A similar situation can occur within the host, upstream of the root ports. The CXL driver performs an additional pass after all the targets have arrived for a region in order to recalculate the bandwidths with possible upstream link being a limiting factor in mind.[3]

Mailboxes

normally in CXL you have to mailbox, one for host>device the other device>host for communication

Sources:

  1. : Compute Express Link Memory Devices — The Linux Kernel documentation

  2. : Compute Express Link Memory Devices — The Linux Kernel documentation

  3. : CXL Access Coordinates Computation — The Linux Kernel documentation